CVE-2024-26721

What it actually does

Incorrect macro calculation of DSC PPS register addresses for PPS >=12 due to unaccounted 12-byte discontinuity from RC Buffer allocation, resulting in invalid read/write of PPS parameters and subsequent DSC corruption.

Why it matters to the business

Systems using Intel integrated graphics with Display Stream Compression enabled may experience visual corruption or instability on affected kernels; high prevalence in Linux distributions increases operational risk for graphics workloads.

How an attack unfolds

An attacker with local access crafts workloads that exercise the DSC PPS register paths for indices 12-16; the erroneous address calculation causes parameter corruption that manifests as display artifacts or driver instability.

How to fix it

Update the Linux kernel to a version containing commit ff5999fb03f467e1e7159f0ddb199c787f7512b9 or later; rebuild and reboot with the corrected macro that adds the required offset for PPS >=12.

How to confirm the fix worked

Confirm the presence of the fix commit in the running kernel source; test DSC-enabled display configurations to verify correct PPS register values and absence of corruption.

Typical attack path

1. Obtain local code execution on an affected Linux system
2. Trigger i915 DSC initialization or mode-setting code paths that reference PPS 12 or higher
3. Observe or induce display corruption or kernel-side faults from invalid register access

How to detect it

Review kernel logs for i915 DSC-related warnings or register access anomalies around PPS handling; correlate with display mode-setting events on Intel hardware.

What your security team should do

• Prioritize kernel updates on systems with Intel i915 graphics and DSC usage
• Monitor upstream stable branches for backports of the corrected macro
• Include the fix in distribution update cycles given the 924-day publication age