CVE-2026-23361
High · 7.8CVSS
7.8
EPSS
0.2%
Published
Mar 25, 2026
CISA due date
—
Cloudanix analysis
A timing problem in how certain hardware interrupts are sent can let a local user on the same machine cause crashes or memory errors that affect attached devices.
- Exploitation
- Local Privilege
- Attacker needs
- Low Privilege
- Complexity
- Low
- Impact
- Data Tampering
- Component
- OS kernel
- Class
- Memory Corruption
- Remediation
- Upgrade
- Effort
- Medium
- Patch risk
- Low
What it actually does
Race between PCI posted write for MSI-X interrupt and outbound ATU unmap allows the write to be lost or misdirected, resulting in host memory corruption or IOMMU translation faults.
Why it matters to the business
Systems using Linux kernel PCI endpoint mode with MSI-X interrupts (storage targets, network devices, accelerators) can experience crashes, I/O failures, or data corruption; the issue has been public for over 200 days with slowly rising exploit probability.
How an attack unfolds
A local attacker with access to an affected endpoint driver invokes dw_pcie_ep_raise_msix_irq(), triggering a writel() that races with the subsequent ATU unmap; if the write loses the race the transaction faults or writes to an invalid address, observable as SMMU translation errors when driving high queue-depth workloads.
How to fix it
Apply the upstream fix that inserts a readl() flush of the MSI-X address before unmapping the ATU entry; rebuild and deploy the patched kernel on all affected systems; where immediate patching is impossible, reduce use of MSI-X vectors or limit endpoint driver exposure.
How to confirm the fix worked
Confirm the readl() flush is present in dw_pcie_ep_raise_msix_irq(); re-run the original fio workload that previously produced SMMU faults and verify absence of translation errors; monitor kernel logs for the arm-smmu-v3 fault signatures during high-queue-depth endpoint activity.
Typical attack path
- Obtain local access or compromise a process that can exercise the PCI endpoint MSI-X path
- Trigger repeated dw_pcie_ep_raise_msix_irq() calls under load (e.g., fio against nvmet-pci-epf)
- Force the posted write to lose the race with ATU unmap, producing IOMMU faults or host memory corruption
How to detect it
Search kernel logs and dmesg for arm-smmu-v3 fault messages containing F_TRANSLATION, unpriv data write, and iova/ip a mismatch values around the time of high-queue-depth endpoint workloads; correlate with processes exercising dw_pcie_ep_raise_msix_irq paths.
What your security team should do
- Prioritize kernel updates on all hosts exposing PCI endpoint functions with MSI-X
- Add kernel log monitoring for arm-smmu-v3 translation faults and iova/ip a mismatch events
- Track EPSS trend and re-evaluate exploitability as the 30-day score continues to rise
The record
In the Linux kernel, the following vulnerability has been resolved: PCI: dwc: ep: Flush MSI-X write before unmapping its ATU entry Endpoint drivers use dw_pcie_ep_raise_msix_irq() to raise an MSI-X interrupt to the host using a writel(), which generates a PCI posted write transaction. There's no completion for posted writes, so the writel() may return before the PCI write completes. dw_pcie_ep_raise_msix_irq() also unmaps the outbound ATU entry used for the PCI write, so the write races with the unmap. If the PCI write loses the race with the ATU unmap, the write may corrupt host memory or cause IOMMU errors, e.g., these when running fio with a larger queue depth against nvmet-pci-epf: arm-smmu-v3 fc900000.iommu: 0x0000010000000010 arm-smmu-v3 fc900000.iommu: 0x0000020000000000 arm-smmu-v3 fc900000.iommu: 0x000000090000f040 arm-smmu-v3 fc900000.iommu: 0x0000000000000000 arm-smmu-v3 fc900000.iommu: event: F_TRANSLATION client: 0000:01:00.0 sid: 0x100 ssid: 0x0 iova: 0x90000f040 ipa: 0x0 arm-smmu-v3 fc900000.iommu: unpriv data write s1 "Input address caused fault" stag: 0x0 Flush the write by performing a readl() of the same address to ensure that the write has reached the destination before the ATU entry is unmapped. The same problem was solved for dw_pcie_ep_raise_msi_irq() in commit 8719c64e76bf ("PCI: dwc: ep: Cache MSI outbound iATU mapping"), but there it was solved by dedicating an outbound iATU only for MSI. We can't do the same for MSI-X because each vector can have a different msg_addr and the msg_addr may be changed while the vector is masked. [bhelgaas: commit log]
Affected packages
| Ecosystem | Package | Introduced | Fixed |
|---|---|---|---|
| openSUSE:Leap 16.0 | dtb-aarch64 | 0 | 6.12.0-160000.28.1 |
| openSUSE:Leap 16.0 | kernel-64kb | 0 | 6.12.0-160000.28.1 |
| openSUSE:Leap 16.0 | kernel-azure | 0 | 6.12.0-160000.28.1 |
| openSUSE:Leap 16.0 | kernel-default | 0 | 6.12.0-160000.28.1 |
| openSUSE:Leap 16.0 | kernel-default-base | 0 | 6.12.0-160000.27.1.160000.2.8 |
| openSUSE:Leap 16.0 | kernel-docs | 0 | 6.12.0-160000.28.1 |
| openSUSE:Leap 16.0 | kernel-kvmsmall | 0 | 6.12.0-160000.28.1 |
| openSUSE:Leap 16.0 | kernel-obs-build | 0 | 6.12.0-160000.28.1 |
| openSUSE:Leap 16.0 | kernel-obs-qa | 0 | 6.12.0-160000.28.1 |
| openSUSE:Leap 16.0 | kernel-rt | 0 | 6.12.0-160000.28.1 |
| openSUSE:Leap 16.0 | kernel-source | 0 | 6.12.0-160000.28.1 |
| openSUSE:Leap 16.0 | kernel-syms | 0 | 6.12.0-160000.28.1 |
| openSUSE:Leap 16.0 | kernel-zfcpdump | 0 | 6.12.0-160000.28.1 |
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