CVE-2025-63384
Medium · 6.5CVSS
6.5
EPSS
0.3%
Published
Nov 10, 2025
CISA due date
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The record
A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.
Affected packages
| Ecosystem | Package | Introduced | Fixed |
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