Cloudanix VulnDB

CVE-2023-31347

None

CVSS

—

EPSS

0.5%

Published

Feb 13, 2024

CISA due date

—

Cloudanix analysis

Monitor only SSVC: Track

A flaw in AMD's secure virtualization technology can let a privileged attacker trick a protected virtual machine into seeing the wrong time, which could quietly break the machine's security protections.

Exploitation
Local Privilege
Attacker needs
High Privilege
Complexity
High
Impact
Data Tampering
Component
Firmware
Class
Improper Input Validation
Remediation
Upgrade
Effort
Medium
Patch risk
Low

What it actually does

Due to improper input validation in Secure_TSC, SEV firmware allows a high-privileged attacker to cause a guest VM to observe an incorrect TSC value when Secure TSC is enabled, resulting in loss of guest integrity.

Why it matters to the business

Virtualized workloads relying on AMD SEV for memory encryption and integrity may experience subtle tampering that undermines trust in guest execution, increasing risk for cloud providers and enterprises running sensitive workloads in confidential VMs.

How an attack unfolds

An attacker with hypervisor or host-level privileges identifies a guest with Secure TSC enabled, then leverages the Secure_TSC code bug to supply crafted TSC data that the guest observes as valid but incorrect, allowing manipulation of time-dependent operations and potential integrity violations without triggering standard SEV protections.

How to fix it

Apply the latest SEV firmware updates from the platform vendor that address the Secure_TSC validation issue; until available, evaluate disabling Secure TSC where integrity requirements allow or isolate affected workloads.

How to confirm the fix worked

Confirm firmware versions on SEV-enabled hosts match vendor-supplied fixed releases; test guest TSC behavior under Secure TSC mode before and after update to verify correct counter observation.

Typical attack path

  1. Obtain high-privileged access to the hypervisor or SEV-enabled host
  2. Locate or create a target guest VM configured with Secure TSC
  3. Trigger the Secure_TSC flaw to inject incorrect TSC observations into the guest
  4. Exploit resulting timing discrepancies to undermine guest integrity checks or time-sensitive security mechanisms

How to detect it

Review hypervisor and SEV firmware logs for unexpected TSC-related events or guest integrity warnings; correlate with privileged access attempts on hosts running Secure TSC-enabled guests.

What your security team should do

  • Inventory all AMD SEV-enabled hosts and identify workloads using Secure TSC
  • Prioritize firmware updates on systems hosting high-value confidential VMs
  • Monitor vendor security bulletins for SEV firmware releases addressing this issue
  • Consider compensating controls such as additional guest-level time synchronization validation until patched

The record

Due to a code bug in Secure_TSC, SEV firmware may allow an attacker with high privileges to cause a guest to observe an incorrect TSC when Secure TSC is enabled potentially resulting in a loss of guest integrity.  

Affected packages

Ecosystem Package Introduced Fixed
Ubuntu:14.04:LTS linux-firmware 0 No fix
Ubuntu:16.04:LTS linux-firmware 0 No fix
Ubuntu:20.04:LTS linux-firmware 0 No fix
Ubuntu:22.04:LTS linux-firmware 0 No fix
Ubuntu:24.04:LTS linux-firmware 0 No fix
Ubuntu:24.10 linux-firmware 0 No fix
Ubuntu:25.04 linux-firmware 0 No fix
Ubuntu:25.10 linux-firmware 0 No fix
Ubuntu:Pro:14.04:LTS linux-firmware 0 No fix
Ubuntu:Pro:16.04:LTS linux-firmware 0 No fix
Ubuntu:Pro:18.04:LTS linux-firmware 0 No fix
Ubuntu:Pro:20.04:LTS linux-firmware 0 No fix

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