CVE-2021-47016

What it actually does

The flaw clears PCC timer 1 configuration bits when clearing the interrupt flag and counter overflow on m68k mvme147 and mvme16x hardware, disabling all subsequent timer interrupts and preventing jiffies updates during kernel initialization.

Why it matters to the business

Legacy Motorola VME-based embedded systems using these boards fail to complete boot, causing prolonged downtime and loss of availability for specialized industrial or scientific deployments.

How an attack unfolds

The defect triggers automatically on every boot of vulnerable kernels on affected hardware; an attacker with the ability to force a reboot on such a system can achieve a persistent denial-of-service condition without further interaction.

How to fix it

Apply the upstream kernel commit that preserves PCC timer configuration bits and enables the timer after IRQ request on mvme16x (consistent with mvme147); rebuild and deploy the fixed kernel image to all affected boards.

How to confirm the fix worked

Boot a patched kernel on target hardware and confirm that timer interrupts continue and calibrate_delay completes; inspect the m68k timer init code to verify config bits are no longer cleared.

Typical attack path

1. Obtain local or physical access to force reboot of target mvme147/mvme16x system
2. Kernel begins initialization and requests the PCC timer IRQ
3. Timer configuration bits are inadvertently cleared
4. No further timer interrupts are delivered
5. calibrate_delay hangs indefinitely waiting for jiffies updates

How to detect it

Review console and kernel boot logs on affected hardware for stalled calibrate_delay messages or absence of timer interrupt activity after the first interrupt; correlate with system hang indicators.

What your security team should do

• Inventory all mvme147 and mvme16x deployments and prioritize kernel updates
• Test patched kernels in a lab environment before production rollout
• Disable or isolate unpatchable legacy hardware until replacement